////////////////////////////////////////////////////////////////////
// Y86 Processor: SEQ Implement
////////////////////////////////////////////////////////////////////

module processor (
    /*AUTOARG*/
   // Outputs
   maddr, wenable, wdata, renable, pc, i_ok, stat,
   // Inputs
   clock, reset, rdata, m_ok, instr
   );

input           clock;     // Clock input
input           reset;     // CPU reset
output [31:0]   maddr;     // Read/Write address 
output          wenable;   // Write enable 
output [31:0]   wdata;     // Write data 
output          renable;   // Read enable 
input  [31:0]   rdata;     // Read data 
input           m_ok;      // Read & write addresses within range 
output [31:0]   pc;        // Instruction address 
input  [47:0]   instr;     // 6 bytes of instruction 
input          i_ok;      // Instruction address within range 
output [2:0]    stat;      // CPU status

/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire                    cnd;                    // From U_execute of execute.v
wire [3:0]              icode;                  // From U_fetch of fetch.v
wire [3:0]              ifun;                   // From U_fetch of fetch.v
wire                    instrErr;               // From U_fetch of fetch.v
wire [3:0]              rA;                     // From U_fetch of fetch.v
wire [3:0]              rB;                     // From U_fetch of fetch.v
wire [31:0]             valA;                   // From U_decode of decode.v
wire [31:0]             valB;                   // From U_decode of decode.v
wire [31:0]             valC;                   // From U_fetch of fetch.v
wire [31:0]             valE;                   // From U_execute of execute.v
wire [31:0]             valM;                   // From U_memory of memory.v
wire [31:0]             valP;                   // From U_fetch of fetch.v
// End of automatics
fetch   U_fetch     ( /*AUTOINST*/
                     // Outputs
                     .pc                (pc[31:0]),
                     .icode             (icode[3:0]),
                     .ifun              (ifun[3:0]),
                     .rA                (rA[3:0]),
                     .rB                (rB[3:0]),
                     .valC              (valC[31:0]),
                     .valP              (valP[31:0]),
                     .instrErr          (instrErr),
                     // Inputs
                     .clock             (clock),
                     .reset             (reset),
                     .instr             (instr[47:0]),
                     .valM              (valM[31:0]),
		     .i_ok		(i_ok),
                     .cnd               (cnd));
decode  U_decode    ( /*AUTOINST*/
                     // Outputs
                     .valA              (valA[31:0]),
                     .valB              (valB[31:0]),
                     // Inputs
                     .clock             (clock),
                     .reset             (reset),
                     .icode             (icode[3:0]),
                     .ifun              (ifun[3:0]),
                     .rA                (rA[3:0]),
                     .rB                (rB[3:0]),
                     .valE              (valE[31:0]),
                     .valM              (valM[31:0]),
                     .cnd               (cnd));
execute U_execute   ( /*AUTOINST*/
                     // Outputs
                     .valE              (valE[31:0]),
                     .cnd               (cnd),
                     // Inputs
                     .clock             (clock),
                     .reset             (reset),
                     .icode             (icode[3:0]),
                     .ifun              (ifun[3:0]),
                     .valC              (valC[31:0]),
                     .valB              (valB[31:0]),
                     .valA              (valA[31:0]));
memory  U_memory    ( /*AUTOINST*/
                     // Outputs
                     .valM              (valM[31:0]),
                     .maddr             (maddr[31:0]),
                     .wenable           (wenable),
                     .wdata             (wdata[31:0]),
                     .renable           (renable),
                     .stat              (stat[2:0]),
                     // Inputs
                     .clock             (clock),
                     .reset             (reset),
                     .icode             (icode[3:0]),
                     .ifun              (ifun[3:0]),
                     .valE              (valE[31:0]),
                     .valA              (valA[31:0]),
                     .valP              (valP[31:0]),
                     .rdata             (rdata[31:0]),
                     .m_ok              (m_ok),
                     .i_ok              (i_ok),
                     .instrErr          (instrErr));

endmodule

